In order to provide information about the power consumption of circuits under design, a variety of power estimation techniques have been developed. Advantageously, such techniques operate at a number of conceptual “levels” of design—from the very basic transistor level to the higher—and more logical—register transfer level (RTL). Since these techniques are relatively mature, an array of commercially available tools have been developed employing their techniques.
Of particular significance, since an RTL description is structurally defined, the power estimate for a circuit so represented is typically performed by aggregating the individual power estimates for its constituent RTL components. Since extensive research has been performed to characterize the individual RTL components, such RTL power estimates are relatively efficient for designs of limited size. Unfortunately, for large designs RTL-based power estimation may be prohibitively slow—especially when a power vs. time profile is required.
In somewhat related efforts, attempts to determine power estimates through functional (or behavioral) methods—without regard to underlying RTL implementations—have met with limited success. Although generally much less accurate than RTL methods, functional methods are quite fast. As a result, their applicability has been limited to fairly coarse-grained design decisions such as comparing algorithmic alternatives.
Accordingly, power estimation techniques that provide the accuracy of RTL methods with the speed of functional techniques would represent a significant advance in the art.